Singapore, Singapore

Pandi Chelvam Marimuthu

This inventor holds 103 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Packaging (CPC class H01L2924-13091). Top assignees: Stats Chippac Pte. Ltd., Jcet Semiconductor (Shaoxing) Co., Ltd.. Active years: 2008-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pandi Chelvam Marimuthu. Retrieved from https://idiyas.com/inventor/pandi-chelvam-marimuthu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 103 

% Patents Active = 100.0

Average Co-Inventor Count = 3.6

ph-index = 15

Forward Citations = 1,018(Granted Patents)

Forward Citations (Not Self Cited) = 912(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Sinagpore, SG (2016)
  • Singapore, SG (2008 - 2024)

Company Filing History:


Years Active: 2008-2026

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Areas of Expertise:
Embedded Wafer Level Chip Scale Package
Fan-Out Package
Ball-Grid Array
Electromagnetic Shielding
Vertical Interconnect Units
Conductive Vias
Thin Die Packaging
Dual-Mold Method
Wafer-Level Chip-Scale Package
Standardized Carrier
PoP Device
Low Profile Packaging
103 patents (USPTO):Explore Patents

Title: Pandi Chelvam Marimuthu: A Pioneer in Semiconductor Innovations

Introduction

Pandi Chelvam Marimuthu is a prominent inventor based in Singapore, with a remarkable portfolio of 101 patents. His groundbreaking work primarily focuses on semiconductor devices, showcasing his commitment to pushing the boundaries of technology. Marimuthu's contributions are instrumental in advancing the capabilities and efficiency of modern electronic devices.

Latest Patents

Among Marimuthu's latest patents is the innovative design of an antenna in an embedded wafer-level ball-grid array package. This patent details a semiconductor device that incorporates a semiconductor die and an encapsulant covering the die. The design features a first conductive layer with an antenna, positioned over a surface of the encapsulant, and a second conductive layer that creates a ground plane on the opposite surface. This unique configuration allows the antenna to be strategically placed within the ground plane’s footprint, enhancing signal integrity. Furthermore, his patent describes a semiconductor device encapsulating a wafer with multiple die, showcasing the removal of an insulating layer through laser drilling to expose the active surfaces of the semiconductor die. These advancements are crucial for the ongoing evolution of semiconductor technology.

Career Highlights

Pandi Chelvam Marimuthu has made significant strides in his career by contributing his expertise to esteemed companies such as Stats Chippac Pte. Ltd. and Jcet Semiconductor (Shaoxing) Co., Ltd. His roles at these organizations have enabled him to refine his skills in semiconductor development, driving forward the creation of cutting-edge technologies that meet the growing demands of the industry.

Collaborations

Throughout his career, Marimuthu has collaborated with talented colleagues, including Yaojian Lin and Il Kwon Shim. These collaborations have played a vital role in fostering an environment of innovation and creativity, allowing for the seamless exchange of ideas and advancements in technology. Teamwork has been a cornerstone of Marimuthu's journey, enhancing the impact of his innovations in the field.

Conclusion

Pandi Chelvam Marimuthu's dedication to innovation in semiconductor devices has set a high standard in the industry. With an extensive array of patents, he continues to influence the landscape of technology, demonstrating the importance of creativity and collaboration in driving progress. His work underscores the endless possibilities that lie within the realm of semiconductor innovations, promising a bright future for electronic advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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