Stats Chippac Pte. Ltd.

Jcet Semiconductor (shaoxing) Co., Ltd.

Stat Chippac Ltd.

Pandi Chelvam Marimuthu

Yaojian Lin

Il Kwon Shim

Kang Chen

Won Kyoung Choi

Nathapong Suthiwongsunthorn

Jose Alvin Caparas

Yu Gu

Seung Wook Yoon

Byung Joon Han

Kock Liang Heng

Hin Hwa Goh

Heinz-Peter Wirtz

Jianmin Fang

Seng Guan Chow

Rajendra D Pendse

Jae Hun Ku

Rui Huang

HeeJo Chi

Robert Charles Frye

Lan H Hoang

Xia Feng

Jun Mo Koo

YoungChul Kim

Shuangwu Huang

Thomas J Strothmann

KyungMoon Kim

JaeHak Yee

Steve Anderson

KooHong Lee

Damien M Pricolo

Reza A Pagaila

Glenn Omandam

See Chian Lim

Andy Chang Bum Yong

Aung Kyaw Oo

Linda Pei Ee Chua

HunTeak Lee

Kai Liu

Sheila Marie L Alvarez

Xusheng Bao

Duk Ju Na

Sze Ping Goh

Yang Kern Jonathan Tan

Byung Tai Do

Heap Hoe Kuan

Jeffrey David Punzalan

Haijing Cao

Antonio Bambalan Dimaano, Jr

Byung Hoon Ahn

Sheila Rima C Magno

JunMo Koo

Dennis Guillermo

Xing Zhao

Ma Shirley Asoy

Chang Beom Yong

Stephen A Murphy

Siew Joo Tan

Shariff Dzafir

Yaojin Lin

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

Semiconductor device and method of forming embedded wafer level chip scale packages

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

Antenna in embedded wafer-level ball-grid array package

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Semiconductor device with encapsulant deposited along sides and surface edge of semiconductor die in embedded WLCSP

A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

Semiconductor device and method of making a wafer-level chip-scale package

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (&#x3bc;m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 &#x3bc;m or less.

A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages

A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Semiconductor device and method of forming double-sided fan-out wafer level package

A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor device and method of using a standardized carrier in semiconductor packaging

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Singapore, Singapore

Pandi Chelvam Marimuthu