The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2016
Filed:
Sep. 23, 2011
Applicants:
Daesup Kim, SujungGu, KR;
Youngjoon Kim, Ichon-si, KR;
Daesik Choi, Seoul, KR;
Inventors:
Assignee:
STATS ChipPAC Pte. Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/24 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/03 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 25/065 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 23/3128 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 25/03 (2013.01); H01L 25/105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16057 (2013.01); H01L 2224/16105 (2013.01); H01L 2224/16108 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/92225 (2013.01); H01L 2224/92242 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06558 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/1815 (2013.01);
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate.