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Jiangyin, China

Sj Semiconductor (Jiangyin) Corporation

USPTO Granted Patents = 84

Forward Citations = 20

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26 inventors (with patents filed for the assignee):

Chengchung Lin (66 out of 68 patents)

Yenheng Chen (52 out of 53 patents)

Chengtar Wu (35 out of 37 patents)

4. Jangshen Lin (28 out of 29 patents)

5. Chengchung Lin (12 out of 12 patents)

6. Yenheng Chen (11 out of 11 patents)

7. Chihon Ho (4 out of 4 patents)

8. Yuedong Qiu (4 out of 4 patents)

9. Mingchih Chen (4 out of 4 patents)

10. Xingtao Xue (4 out of 4 patents)

11. Hailin Zhao (3 out of 3 patents)

12. Yayuan Xue (3 out of 3 patents)

13. Jiashan Yin (3 out of 3 patents)

14. Zuyuan Zhou (3 out of 3 patents)

15. Hanlung Tsai (3 out of 3 patents)

Core Competencies:

Fan-Out Structures

Antenna Modules

3D Integration

Wafer-Level Packaging

Chip Packaging

Packaging Methods

LED Packaging

Thermal Management

Electromagnetic Waves

Stacked Packages

Heat Sink Structures

Semiconductor Structures

84 patents: Sort by Forward Citations

1. 12757749 - Packaging structure having organic interposer layer and method for manufacturing same (2026-10-06),

2. 12740444 - Method for manufacturing a 2.5D/3D electronic packaging structure by embedding a wafer into a cavity of a glass substrate (2026-09-15),

3. 12721161 - Thermally conductive semiconductor packaging structure and method for preparing same (2026-08-25),

4. 12713981 - STACKED MEMORY POP STRUCTURE AND PACKAGING METHOD THEREOF (2026-08-18),

5. 12713968 - FAN-OUT WAFER-LEVEL PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME (2026-08-18),

6. 12713967 - 3D FAN-OUT PACKAGING STRUCTURE OF INTERCONNECTION SYSTEM WITH ULTRA-HIGH DENSITY AND METHOD FOR MANUFACTURING THE SAME (2026-08-18),

7. 12708056 - Fan-out packaging structure and method for manufacturing same (2026-08-11),

8. 12702079 - Fan-out system-level packaging structure and packaging method (2026-08-04),

9. 12677703 - Three-dimensional fan-out memory package with conductive pillars and packaging method thereof (2026-07-07),

10. 12660631 - Fan-out packaging structure and method for manufacturing same (2026-06-16),

11. 12616064 - Three-dimensional fan-out integrated package structure, packaging method thereof, and wireless headset (2026-04-28),

12. 12610868 - Fan-out stacked semiconductor package structure and packaging method thereof (2026-04-21),

13. 12588544 - Packaging structure and packaging method (2026-03-24),

14. 12550740 - Chip packaging structure and method for manufacturing same (2026-02-10),

15. 12525581 - Pop structure of three-dimensional fan-out memory and packaging method thereof (2026-01-13),

Company Overview

Sj Semiconductor (Jiangyin) Corporation specializes in advanced semiconductor packaging solutions, focusing on innovative technologies such as fan-out structures and wafer-level packaging. The company is dedicated to enhancing chip packaging methods, including thermal management and LED packaging, to meet the evolving demands of the semiconductor industry. Located in Jiangyin, China, Sj Semiconductor plays a pivotal role in the development of 3D integration and antenna modules, contributing to the advancement of high-performance electronic devices.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

84 Patents

#1 in Jiangyin

#396 in China

#9,061 in the World

Jiangyin, China

Sj Semiconductor (Jiangyin) Corporation

Forward Citations = 20

26 inventors:

Chengchung Lin (66 out of 68 patents)

Yenheng Chen (52 out of 53 patents)

Chengtar Wu (35 out of 37 patents)

4. Jangshen Lin (28 out of 29 patents)

5. Chengchung Lin (12 out of 12 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Sj Semiconductor (Jiangyin) Corporation. Retrieved from https://idiyas.com/company/sj-semiconductor-jiangyin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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