The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Apr. 11, 2023
Applicant:

Sj Semiconductor(jiangyin) Corporation, Jiangyin City, CN;

Inventors:

Yenheng Chen, Jiangyin City, CN;

Chengchung Lin, Jiangyin City, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/5389 (2013.01); H01L 24/04 (2013.01); H01L 24/13 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A fan-out packaging structure includes a first dielectric layer, a first antenna layer, a first packaging layer, a first redistribution layer, a second packaging layer, a second redistribution layer, a first conductive pillar, a second conductive pillar, a chip, and a solder bump. Two ends of the first conductive pillar connect to the first antenna layer and the second antenna layer; two ends of the second conductive pillar connect to the second antenna layer and the second redistribution layer. The chip is in the second packaging layer, and electrodes of the chip are electrically connected to the second redistribution layer, and a chip backside layer is bonded to the first redistribution layer; the solder bump is located over the second redistribution layer. There is only one support carrier for multiple layers of antennas and the chip, reducing the package size. The backside layer isolates the antennas from the chip interference.


Find Patent Forward Citations

Chen, Yenheng. (2026). Fan-out packaging structure and method for manufacturing same (U.S. Patent No. 12660631). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12660631

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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