The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Apr. 10, 2023
Applicant:

Sj Semiconductor(jiangyin) Corporation, Jiangyin, CN;

Inventors:

Chengchung Lin, Jiangyin, CN;

Jin Yang, Jiangyin, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H05K 1/0271 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A chip packaging structure and a method for manufacturing are disclosed, including a semiconductor chip, a device layer, and a warpage compensation layer, which is bonded to the device layer. The warpage compensation layer has a thermal expansion coefficient matching that of the semiconductor chip, the mismatch in coefficients of thermal expansion between the substrate and the semiconductor chip can be compensated, thereby reducing or eliminating warpage. The thermal expansion coefficient of the warpage compensation layer is also close to that of the semiconductor chip, so they form a structure that has an in-between thermal expansion coefficient, which creates synchronous tensions or stress on top and bottom surfaces of the substrate to prevent it from bending toward one side.


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