The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Apr. 07, 2023
Applicant:

Sj Semiconductor(jiangyin) Corporation, Jiangyin City, CN;

Inventors:

Chengchung Lin, Jiangyin City, CN;

Jin Yang, Jiangyin City, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/63 (2026.01); H10W 70/60 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 99/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/635 (2026.01); H10W 70/611 (2026.01); H10W 72/013 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 99/00 (2026.01); H10W 90/734 (2026.01);
Abstract

A 2.5D/3D electronic packaging structure and a method for manufacturing it are disclosed. The method includes: disposing a metal array over a wafer, fixing a first die and a second die to the metal array; removing a portion of the wafer to expose bottom surfaces of the first die and the second die; providing a glass substrate, forming a cavity on the surface of the glass substrate; forming vias through the glass substrate, filling the vias with metal materials to form metal pillars; forming first solder pads each at a first end of one of the metal pillars, and forming second solder pads each at a second end of that metal pillar; embedding the wafer in the cavity, and connecting the first solder pads to the first die and the second die, and connecting the second solder pads to an organic substrate.


Find Patent Forward Citations

Lin, Chengchung. (2026). Method for manufacturing a 2.5d/3d electronic packaging structure by embedding a wafer into a cavity of a glass substrate (U.S. Patent No. 12740444). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12740444

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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