The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Apr. 26, 2023
Applicant:

Sj Semiconductor(jiangyin) Corporation, Jiangyin City, CN;

Inventors:

Yenheng Chen, Jiangyin City, CN;

Chengchung Lin, Jiangyin City, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H10B 80/00 (2026.01); H10D 12/00 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/27 (2025.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 70/093 (2026.01); H10W 70/65 (2026.01); H10W 74/016 (2026.01); H10W 74/117 (2026.01); H10W 90/24 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 72/07252 (2026.01); H10W 72/07253 (2026.01); H10W 72/221 (2026.01); H10W 72/234 (2026.01); H10W 72/877 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01);
Abstract

A three-dimensional fan-out memory package structure and a packaging method are disclosed. The package structure includes a three-dimensional fan-out memory package unit, which includes: a memory chip stack having at least two memory chips laminated in a stepped configuration, each memory chip is provided with a bonding pad; first metal connection pillars formed on the bonding pads; second metal connection pillars; a first encapsulating layer; a first rewiring layer formed on a back side of the memory chip stack; a second rewiring layer formed over a front side of the memory chip stack; and metal bumps. The package structure further includes: at least one peripheral circuit chip electrically connected with the first rewiring layer; and a second encapsulating layer, which encapsulates the peripheral circuit chip. The package structure allows for high-density and high-integration of line width/line spacing. The process time can be shortened, and the efficiency is high.


Find Patent Forward Citations

Chen, Yenheng. (2026). Three-dimensional fan-out memory package with conductive pillars and packaging method thereof (U.S. Patent No. 12677703). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12677703

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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