For the Inventor, By the Inventor

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Sunnyvale, CA, United States of America

Fasl LLC

USPTO Granted Patents = 30

% Expired Patents = 23.3

Forward Citations = 606

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53 inventors (with patents filed for the assignee):

Hidehiko Shiraiwa (15 out of 73 patents)

Arvind Halliyal (10 out of 82 patents)

Tazrien Kamal (9 out of 41 patents)

4. Mark T Ramsbey (8 out of 162 patents)

5. Jaeyong Park (7 out of 23 patents)

6. Jean Y Yang (6 out of 49 patents)

7. Rinji Sugino (5 out of 30 patents)

8. Amir Hossein Jafarpour (4 out of 6 patents)

9. Pau-Ling Chen (4 out of 70 patents)

10. Darlene G Hamilton (4 out of 66 patents)

11. Minh Van Ngo (3 out of 292 patents)

12. Inkuk Kang (3 out of 22 patents)

13. Kazuhiro Kurihara (3 out of 74 patents)

14. Yu Nan Sun (3 out of 109 patents)

15. Hiroyuki Ogawa (2 out of 174 patents)

Core Competencies:

Flash Memory

Charge-Trapping

Polymer Memory Cells

Semiconductor Device

ONO Fabrication

Electrostatic Discharge

Voltage Compensation

Nitride Layer

Hot Carrier Injection

Memory Device

Junction Leakage

Reverse LDD

30 patents: Sort by Forward Citations

1. 7394125 - Recessed channel with separated ONO memory device (2008-07-01),

2. 7122853 - Method to improve yield and simplify operation of polymer memory cells (2006-10-17),

3. 7098546 - Alignment marks with salicided spacers between bitlines for alignment signal improvement (2006-08-29),

4. 7074677 - Memory with improved charge-trapping dielectric layer (2006-07-11),

5. 7067377 - Recessed channel with separated ONO memory device (2006-06-27),

6. 7037780 - Semiconductor memory device and method of fabricating the same (2006-05-02),

7. 7033957 - ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices (2006-04-25),

8. 7019366 - Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance (2006-03-28),

9. 7009887 - Method of determining voltage compensation for flash memory devices (2006-03-07),

10. 6984563 - Floating gate semiconductor component and method of manufacture (2006-01-10),

11. 6979577 - Method and apparatus for manufacturing semiconductor device (2005-12-27),

12. 6977195 - Test structure for characterizing junction leakage current (2005-12-20),

13. 6969886 - ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices (2005-11-29),

14. 6958511 - Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen (2005-10-25),

15. 6955965 - Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device (2005-10-18),

Company Overview

Fasl LLC, based in Sunnyvale, California, specializes in advanced technology solutions focusing on software development and data analytics. The company is dedicated to creating innovative applications that enhance operational efficiency and drive digital transformation across various industries. With a strong emphasis on research and development, Fasl LLC explores cutting-edge technologies to address complex challenges, positioning itself as a key player in the technology landscape.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

30 Patents

#142 in Sunnyvale, CA

#2,680 in California

#11,272 in US

#21,888 in the World

Sunnyvale, CA, United States of America

Fasl LLC

Forward Citations = 606

53 inventors:

Hidehiko Shiraiwa (15 out of 73 patents)

Arvind Halliyal (10 out of 82 patents)

Tazrien Kamal (9 out of 41 patents)

4. Mark T Ramsbey (8 out of 162 patents)

5. Jaeyong Park (7 out of 23 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Fasl LLC. Retrieved from https://idiyas.com/company/fasl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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