The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2005
Filed:
Oct. 06, 2003
Arvind Halliyal, Cupertino, CA (US);
Amir H. Jafarpour, Pleasanton, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Tazrien Kamal, San Jose, CA (US);
Mark Ramsbey, Sunnyvale, CA (US);
Jaeyong Park, Sunnyvale, CA (US);
Arvind Halliyal, Cupertino, CA (US);
Amir H. Jafarpour, Pleasanton, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Tazrien Kamal, San Jose, CA (US);
Mark Ramsbey, Sunnyvale, CA (US);
Jaeyong Park, Sunnyvale, CA (US);
FASL, LLC, Sunnyvale, CA (US);
Abstract
Process of fabricating multi-bit charge trapping dielectric flash memory device, including forming on a semiconductor substrate a bottom oxide layer to define a substrate/oxide interface, in which the bottom oxide layer includes a first oxygen concentration and a first nitrogen concentration; and adding a quantity of nitrogen to the bottom oxide layer, whereby the bottom oxide layer includes a first region adjacent the charge storage layer and a second region adjacent the substrate/oxide interface, the second region having a second oxygen concentration and a second nitrogen concentration, in which the second nitrogen concentration exceeds the first nitrogen concentration, provided that the second nitrogen concentration does not exceed the second oxygen concentration. In one embodiment, the first nitrogen concentration is substantially zero.