Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance

Abstract

More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.