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For the Inventor, By the Inventor

Wappingers Falls, NY, United States of America

Michael Vincent Aquilino

This inventor holds 27 USPTO granted patents and 1 published patent application, primarily in Semiconductor Devices. Top assignees: Globalfoundries Inc., International Business Machines Corporation, Globalfoundries U.S. Inc.. Active years: 2011-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Michael Vincent Aquilino. Retrieved from https://idiyas.com/inventor/michael-vincent-aquilino

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27 

% Patents Active = 77.8

Average Co-Inventor Count = 5.0

ph-index = 6

Forward Citations = 106(Granted Patents)


Location History:

  • Hopewell Junction, NY (US) (2013 - 2015)
  • Wappingers Falls, NY (US) (2011 - 2019)
  • Saratoga Springs, NY (US) (2017 - 2019)
  • Gansevoort, NY (US) (2019 - 2021)

Company Filing History:

goldMedal14 out of 5,671 
 
Globalfoundries Inc.
 patents
silverMedal11 out of 166,351 
 
International Business Machines Corporation
 patents
bronzeMedal3 out of 1,090 
 
Globalfoundries U.S. Inc.
 patents
4. 1 out of 1,060 
 
Globalfoundries Singapore Pte. Ltd.
 patents
where one patent can have more than one assignee

Years Active: 2011-2021

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Areas of Expertise:
Field-Effect Transistors
FinFET Technology
Epitaxial Structures
Gate Height Loss
Trench Isolation
Defect Reduction
High-K Metal Gate
Self-Aligned Contacts
CMOS Devices
Insulating Spacer
EPI Short Prevention
Facet-Less Epitaxy
27 patents (USPTO):Explore Patents
1. 11101364 - Field-effect transistors with diffusion blocking spacer sections (2021-08-24),
2. 10971625 - Epitaxial structures of a semiconductor device having a wide gate pitch (2021-04-06),
3. 10930549 - Cap structure (2021-02-23),
4. 10833160 - Field-effect transistors with self-aligned and non-self-aligned contact openings (2020-11-10),
5. 10644156 - Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices (2020-05-05),
6. 10522639 - Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device (2019-12-31),
7. 10460986 - Cap structure (2019-10-29),
8. 10453751 - Tone inversion method and structure for selective contact via patterning (2019-10-22),
9. 10418455 - Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device (2019-09-17),
10. 10340142 - Methods, apparatus and system for self-aligned metal hard masks (2019-07-02),
11. 10325819 - Methods, apparatus and system for providing a pre-RMG replacement metal contact for a finFET device (2019-06-18),
12. 10269654 - Methods, apparatus and system for replacement contact for a finFET device (2019-04-23),
13. 10204797 - Methods, apparatus, and system for reducing step height difference in semiconductor devices (2019-02-12),
14. 10177154 - Structure and method to prevent EPI short between trenches in FinFET eDRAM (2019-01-08),
15. 10049985 - Contact line having insulating spacer therein and method of forming same (2018-08-14),

Title: The Innovative Contributions of Michael Vincent Aquilino

Introduction: Michael Vincent Aquilino is a remarkable inventor based in Wappingers Falls, NY, known for his extensive work in semiconductor technology. With a portfolio of 27 patents, Aquilino has made significant strides in the field of field-effect transistors and semiconductor devices. His contributions have proven invaluable to the industry, enhancing the efficiency and performance of electronic components.

Latest Patents: Among his latest inventions are two notable patents: first, the development of field-effect transistors with diffusion blocking spacer sections. This innovation involves a gate structure arranged over an active region composed of semiconductor material, featuring a first sidewall spacer adjacent to the gate and a second spacer strategically placed between the first spacer and the active region, utilizing a low-k dielectric material. The second invention addresses epitaxial structures of a semiconductor device with a wide gate pitch. This patent outlines a semiconductor device that incorporates an array of active regions and gate stacks, along with an active pillar that separates two remarkably uniform epitaxial structures, ensuring precise contact structure placement over the active pillar.

Career Highlights: Michael has built a successful career, working for prestigious companies such as GlobalFoundries Inc. and IBM. His tenure at these organizations has allowed him to contribute to cutting-edge technologies and innovations in semiconductor manufacturing.

Collaborations: Throughout his professional journey, Aquilino has collaborated with esteemed colleagues, including Daniel J. Jaeger and Patrick D. Carpenter. These collaborative efforts have facilitated the development of advanced technologies and furthered the field of semiconductor engineering.

Conclusion: Michael Vincent Aquilino's innovative spirit and dedication to the advancement of semiconductor technologies are evident through his numerous patents and impactful collaborations. His work continues to shape the electronic industry, paving the way for more efficient and high-performing devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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