The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Mar. 12, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jinsheng Gao, Clifton Parkl, NY (US);

Daniel Jaeger, Saratoga Springs, NY (US);

Michael Aquilino, Gansevoort, NY (US);

Patrick Carpenter, Saratoga Springs, NY (US);

Jiehui Shu, Clifton Park, NY (US);

Pei Liu, Clifton Park, NY (US);

Jinping Liu, Ballston Lake, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0337 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 29/6653 (2013.01); H01L 29/66553 (2013.01);
Abstract

At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.


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