The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Apr. 17, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Michael Aquilino, Gansevoort, NY (US);

Daniel Jaeger, Saratoga Springs, NY (US);

Naved Siddiqui, Malta, NY (US);

Jessica Dechene, Watervliet, NY (US);

Daniel J. Dechene, Watervliet, NY (US);

Shreesh Narasimha, Charlotte, NC (US);

Natalia Borjemscaia, Greensboro, NC (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/82 (2006.01); H01L 21/033 (2006.01); H01L 21/027 (2006.01); H01L 21/306 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41775 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 27/088 (2013.01); H01L 29/401 (2013.01);
Abstract

Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.


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