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Beacon, NY, United States of America

Shreesh Narasimha

USPTO Granted Patents = 115 (Patent Applications = 39)

EPO Patents = 1 (Patent Applications = 1)

Average Co-Inventor Count = 4.6

ph-index = 12

Forward Citations = 694(Granted Patents)

Forward Citations (Not Self Cited) = 602(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Hopewell Jct., NY (US) (2012)
Hopewell Junction, NY (US) (2011 - 2014)
Yorktown Heights, NY (US) (2012 - 2015)
Charlotte, NC (US) (2020)
Beacon, NY (US) (2004 - 2021)
Clifton Park, NY (US) (2021)

Company Filing History:

102 out of 164,135

International Business Machines Corporation

10 out of 5,671

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

4. 1 out of 935

Globalfoundries U.S. Inc.

Years Active: 2004-2021

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Areas of Expertise:

High-K Dielectric

Field-Effect Transistors

Semiconductor Structures

Shallow Trench Isolation

Integrated Passive Structures

Dual Shallow Trench Isolation

Planar Polysilicon Regions

Epitaxial Buffer Layer

Complementary Metal Oxide Semiconductor

Gate Structures

Threshold Voltage Adjustment

Nanowire Field Effect Transistors

115 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11101357 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2021-08-24),

2. 11056398 - Forming interconnect without gate cut isolation blocking opening formation (2021-07-06),

3. 10833160 - Field-effect transistors with self-aligned and non-self-aligned contact openings (2020-11-10),

4. 10734492 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2020-08-04),

5. 10580686 - Semiconductor structure with integrated passive structures (2020-03-03),

6. 10381452 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-08-13),

7. 10374048 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-08-06),

8. 10367072 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-07-30),

9. 10242906 - Semiconductor structure with integrated passive structures (2019-03-26),

10. 10083878 - Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile (2018-09-25),

11. 10074571 - Device with decreased pitch contact to active regions (2018-09-11),

12. 10032862 - Semiconductor structure with integrated passive structures (2018-07-24),

13. 9922831 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2018-03-20),

14. 9859122 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2018-01-02),

15. 9837319 - Asymmetric high-K dielectric for reducing gate induced drain leakage (2017-12-05),

Title: The Innovative Journey of Inventor Shreesh Narasimha

Introduction: Shreesh Narasimha, a talented inventor based in Beacon, NY, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents: Shreesh Narasimha holds several patents in the areas of artificial intelligence, renewable energy, and medical devices, showcasing his diverse range of expertise and creativity.

Career Highlights: Throughout his career, Shreesh Narasimha has worked with leading tech companies to develop cutting-edge solutions that have revolutionized industries. His passion for innovation and problem-solving has led to the creation of products that have improved the lives of many.

Collaborations: Shreesh Narasimha has collaborated with top researchers, engineers, and scientists from around the world to bring his ideas to life. His ability to work in multidisciplinary teams has resulted in successful projects that have received international recognition.

Conclusion: In conclusion, Shreesh Narasimha's relentless pursuit of innovation and his commitment to pushing the boundaries of technology make him a true visionary in the world of inventions. His impact on the industry is profound, and his legacy will continue to inspire future generations of inventors.

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