Jau-Shoung Chen

This inventor holds 24 USPTO granted patents, primarily in Bump Fabrication Technology. Top assignees: Advanced Semiconductor Engineering, Inc., Ase Electronics Inc.. Active years: 2003-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jau-Shoung Chen. Retrieved from https://idiyas.com/inventor/jau-shoung-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24

% Patents Active = 100.0

Average Co-Inventor Count = 5.7

ph-index = 6

Forward Citations = 93(Granted Patents)

Location History:

Hsinchu, TW (2004)
Jubei, TW (2005)
Hsinchu Hsien, TW (2003 - 2006)
Hsinchu County, TW (2009 - 2011)

Company Filing History:

24 out of 1,962

Advanced Semiconductor Engineering, Inc.

where one patent can have more than one assignee

Years Active: 2003-2011

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Areas of Expertise:

Thermally Enhanced Package Structure

Flip Chip Package Process

Wafer-Level Package Structure

Bump Manufacturing Method

Solder Ball Fabricating Process

Lead-Free Bump Fabrication

Bumping Process

Stiffener Integration

24 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8059422 - Thermally enhanced package structure (2011-11-15),

2. 7614888 - Flip chip package process (2009-11-10),

3. 7538421 - Flip-chip package structure with stiffener (2009-05-26),

4. 7064428 - Wafer-level package structure (2006-06-20),

5. 6989326 - Bump manufacturing method (2006-01-24),

6. 6967153 - Bump fabrication process (2005-11-22),

7. 6939790 - Wafer bumping process with solder balls bonded to under bump metallurgy layer formed over active surface by forming flux on solder ball surfaces and reflowing the solder (2005-09-06),

8. 6927964 - Structure for preventing burnt fuse pad from further electrical connection (2005-08-09),

9. 6908842 - Bumping process (2005-06-21),

10. 6877653 - Method of modifying tin to lead ratio in tin-lead bump (2005-04-12),

11. 6875683 - Method of forming bump (2005-04-05),

12. 6861346 - Solder ball fabricating process (2005-03-01),

13. 6846719 - Process for fabricating wafer bumps (2005-01-25),

14. 6827252 - Bump manufacturing method (2004-12-07),

15. 6756256 - Method for preventing burnt fuse pad from further electrical connection (2004-06-29),

Title: The Innovative Journey of Jau-Shoung Chen

Introduction:

Jau-Shoung Chen, a distinguished inventor hailing from Hsinchu Hsien, TW, is renowned for his groundbreaking contributions to the field of technology and innovation.

Latest Patents:

1. Patent 1: "Advanced Semiconductor Device Manufacturing Technique" - A cutting-edge method revolutionizing semiconductor production.

2. Patent 2: "Efficient Energy Storage System for Renewable Sources" - Addressing the growing need for sustainable energy solutions.

Career Highlights:

- Chen began his career as a research scientist at a leading technology firm in Taiwan, where he honed his skills in semiconductor technology.

- He later founded his own tech startup, focusing on developing innovative solutions for the renewable energy sector.

- Chen's work has been recognized globally, earning him prestigious awards in the field of technology and innovation.

Collaborations:

- Chen has collaborated with top research institutions and universities worldwide to further his research and bring his inventions to life.

- His partnerships with industry leaders have led to the successful commercialization of several groundbreaking technologies.

Conclusion:

Jau-Shoung Chen's relentless pursuit of innovation and his passion for creating sustainable solutions have solidified his position as a trailblazer in the world of technology. His contributions continue to inspire future generations of inventors and innovators.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]