The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Dec. 19, 2002
Ho-ming Tong, Taipei, TW;
Chun-chi Lee, Kaohsiung, TW;
Jen-kuang Fang, Pingtung Hsien, TW;
Min-lung Huang, Kaohsiung, TW;
Jau-shoung Chen, Hsinchu Hsien, TW;
Ching-huei Su, Kaohsiung, TW;
Chao-fu Weng, Tainan, TW;
Yung-chi Lee, Kaohsiung, TW;
Yu-chen Chou, Kaohsiung, TW;
Tsung-hua Wu, Kaohsiung Hsien, TW;
Su Tao, Kaohsiung, TW;
Ho-Ming Tong, Taipei, TW;
Chun-Chi Lee, Kaohsiung, TW;
Jen-Kuang Fang, Pingtung Hsien, TW;
Min-Lung Huang, Kaohsiung, TW;
Jau-Shoung Chen, Hsinchu Hsien, TW;
Ching-Huei Su, Kaohsiung, TW;
Chao-Fu Weng, Tainan, TW;
Yung-Chi Lee, Kaohsiung, TW;
Yu-Chen Chou, Kaohsiung, TW;
Tsung-Hua Wu, Kaohsiung Hsien, TW;
Su Tao, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.