The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2005
Filed:
Feb. 20, 2003
Ho-ming Tong, Taipei, TW;
Chun-chi Lee, Kaohsiung, TW;
Jen-kuang Fang, Pingtung Hsien, TW;
Min-lung Huang, Koahsiung, TW;
Jau-shoung Chen, Hsinchu Hsien, TW;
Ching-huei Su, Kaohsiung, TW;
Chao-fu Weng, Tainan, TW;
Yung-chi Lee, Kaohsiung, TW;
Yu-chen Chou, Kaohsiung, TW;
Tsung-hua Wu, Kaohsing Hsien, TW;
Su Tao, Kaohsiung, TW;
Ho-Ming Tong, Taipei, TW;
Chun-Chi Lee, Kaohsiung, TW;
Jen-Kuang Fang, Pingtung Hsien, TW;
Min-Lung Huang, Koahsiung, TW;
Jau-Shoung Chen, Hsinchu Hsien, TW;
Ching-Huei Su, Kaohsiung, TW;
Chao-Fu Weng, Tainan, TW;
Yung-Chi Lee, Kaohsiung, TW;
Yu-Chen Chou, Kaohsiung, TW;
Tsung-Hua Wu, Kaohsing Hsien, TW;
Su Tao, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.