The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2004
Filed:
Feb. 20, 2003
Ho-Ming Tong, Taipei, TW;
Chun-Chi Lee, Kaohsiung, TW;
Jen-Kuang Fang, Pingtung Hsien, TW;
Min-Lung Huang, Kaohsiung, TW;
Jau-Shoung Chen, Hsinchu Hsien, TW;
Ching-Huei Su, Kaohsiung, TW;
Chao-Fu Weng, Tainan, TW;
Yung-Chi Lee, Kaohsiung, TW;
Yu-Chen Chou, Kaohsiung, TW;
Tsung-Hua Wu, Kaohsiung Hsien, TW;
Su Tao, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.