The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2011
Filed:
Jul. 31, 2008
Ho-ming Tong, Taipei, TW;
Shin-hua Chao, Kaohsiung, TW;
Ming-chiang Lee, Kaohsiung, TW;
Tai-yuan Huang, Kaohsiung County, TW;
Chao-yuan Liu, Kaohsiung, TW;
Yung-cheng Huang, Kaohsiung, TW;
Teck-chong Lee, Kaohsiung, TW;
Jen-chieh Kao, Kaohsiung, TW;
Jau-shoung Chen, Hsinchu County, TW;
Ho-Ming Tong, Taipei, TW;
Shin-Hua Chao, Kaohsiung, TW;
Ming-Chiang Lee, Kaohsiung, TW;
Tai-Yuan Huang, Kaohsiung County, TW;
Chao-Yuan Liu, Kaohsiung, TW;
Yung-Cheng Huang, Kaohsiung, TW;
Teck-Chong Lee, Kaohsiung, TW;
Jen-Chieh Kao, Kaohsiung, TW;
Jau-Shoung Chen, Hsinchu County, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
ASE Electronics Inc., Kaohsiung, TW;
Abstract
A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.