Howard Smith Landis

This inventor holds 50 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Design (CPC class H01L). Top assignees: International Business Machines Corporation, Globalfoundries U.S. 2 LLC. Active years: 1991-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Howard Smith Landis. Retrieved from https://idiyas.com/inventor/howard-smith-landis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 50 (Patent Applications = 2)

% Patents Active = 44.0

Average Co-Inventor Count = 2.7

ph-index = 9

Forward Citations = 414(Granted Patents)

Forward Citations (Not Self Cited) = 392(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Underhill, VT (US) (1991 - 2015)
Essex Junction, VT (US) (2015 - 2019)

Company Filing History:

49 out of 166,351

International Business Machines Corporation

patents

1 out of 59

Globalfoundries U.S. 2 LLC

patents

Years Active: 1991-2019

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Areas of Expertise:

Integrated Circuit

Dummy Fill

Layout Optimization

Dielectric Reliability

Optical Proximity Correction

Silicon on Insulator

Metallization

Parasitic Capacitance

Chip Connections

Pattern Density

Crack Trapping

Aluminum to Copper Migration

50 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10254642 - Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects (2019-04-09),

2. 9977325 - Modifying design layer of integrated circuit (IC) (2018-05-22),

3. 9170482 - Trimming of dummy fill shapes holes to affect near-neighbor dummy fill shapes with built-in optical proximity corrections for semiconductor applications (2015-10-27),

4. 8954901 - Parameter variation improvement (2015-02-10),

5. 8839177 - Method and system allowing for semiconductor design rule optimization (2014-09-16),

6. 8796133 - Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections (2014-08-05),

7. 8739078 - Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications (2014-05-27),

8. 8507346 - Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer (2013-08-13),

9. 8423945 - Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes (2013-04-16),

10. 8299775 - Current-aligned auto-generated non-equiaxial hole shape for wiring (2012-10-30),

11. 8288821 - SOI (silicon on insulator) substrate improvements (2012-10-16),

12. 8176447 - Formation of masks/reticles having dummy features (2012-05-08),

13. 8138607 - Metal fill structures for reducing parasitic capacitance (2012-03-20),

14. 8089126 - Method and structures for improving substrate loss and linearity in SOI substrates (2012-01-03),

15. 7930667 - System and method of automated wire and via layout optimization description (2011-04-19),

Title: Howard Smith Landis - The Innovative Mind from Underhill

Introduction: Howard Smith Landis, a distinguished inventor hailing from Underhill, VT, has made significant contributions to the field of technology with his groundbreaking inventions.

Latest Patents: Landis holds several patents in various technological domains, showcasing his versatility and creativity in innovation.

Career Highlights: With a career spanning over two decades, Landis has consistently pushed the boundaries of technology, revolutionizing the industry with his forward-thinking ideas and solutions.

Collaborations: Throughout his career, Landis has collaborated with leading tech companies and research institutions, fostering a culture of innovation and excellence in all his projects.

Conclusion: Howard Smith Landis stands as a beacon of innovation, inspiring future generations of inventors to think outside the box and pursue their creative visions relentlessly.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

2 patents pending: