The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2012
Filed:
Aug. 26, 2009
Alan Bernard Botula, Essex Junction, VT (US);
David S. Collins, Williston, VT (US);
Alvin Jose Joseph, Williston, VT (US);
Howard Smith Landis, Underhill, VT (US);
James Albert Slinkman, Montpelier, VT (US);
Alan Bernard Botula, Essex Junction, VT (US);
David S. Collins, Williston, VT (US);
Alvin Jose Joseph, Williston, VT (US);
Howard Smith Landis, Underhill, VT (US);
James Albert Slinkman, Montpelier, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.