The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Jul. 20, 2012
Griselda Bonilla, Fishkill, NY (US);
Timothy H. Daubenspeck, Colchester, VT (US);
Mark C. H. Lamorey, South Burlington, VT (US);
Howard S. Landis, Underhill, VT (US);
Xiao HU Liu, Briarcliff Manor, NY (US);
David L. Questad, Hopewell Junction, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
David B. Stone, Jericho, VT (US);
Griselda Bonilla, Fishkill, NY (US);
Timothy H. Daubenspeck, Colchester, VT (US);
Mark C. H. Lamorey, South Burlington, VT (US);
Howard S. Landis, Underhill, VT (US);
Xiao Hu Liu, Briarcliff Manor, NY (US);
David L. Questad, Hopewell Junction, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
David B. Stone, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.