International Business Machines Corporation

Globalfoundries U.S. 2 LLC

Howard Smith Landis

Jeanne-Tania Sucharitaves

Timothy G Dunham

Anthony K Stamper

Mark Alan Lavin

William C Leipold

Ezra D B Hall

John Edward Cronin

Griselda Bonilla

Thomas M Shaw

David S Collins

Bette L Bergman Reuter

David P Parker

Edward J Nowak

Brent A Anderson

Son Van Nguyen

Alvin Jose Joseph

James Albert Slinkman

Jeanne P Bickford

William Thomas Motsiff

Alan Bernard Botula

James Patrick Doyle

Michael Wayne Lane

Rosemary A Previti-Kelly

Veeresh Vidyadhar Deshpande

Eric Gerhard Liniger

Carter W Kaanta

Peter John Geiss

Thomas Benjamin Faure

Amit Kumar

Xio Hu Liu

Arun Sankar Mampazhy

Neelima Mandloi

Jeffrey P Gambino

John J Ellis-Monaghan

Steven H Voldman

Oleg Gluschenkov

Timothy Harrison Daubenspeck

James William Adkisson

Zhong-Xiang He

Matthew Earl Colburn

Kai D Feng

Hanyi Ding

Xiao Hu Liu

Xuefeng Liu

David Brian Stone

David L Questad

Paul Christian Parries

Michael Joseph Zierak

Donald M Kenney

Natalie Barbara Feilchenfeld

Robert Michael Geffken

Scott David Halle

Mark C H Lamorey

Allen H Gabor

Matthew J Rutten

Mark Steven Styduhar

Donald J Samuels

Benjamin T Voegeli

Paul M Feeney

Martin Burkhardt

Brian J Machesney

Shaw-Ning Mei

Helen Wang

Michael L Kerbaugh

Florian Braun

John F Rembetski

Sally J Yankee

Roger J Yerdon

Edward J Vishnesky

Charles H Windisch, Jr

Pavan Y Bashaboina

Brent A Goplen

Mark D Aubel

Paul C Buschner

Janet M Wilson

Bao T Hwang

John W Andrews

James M Tyler

Geoffrey K Abbott

Geoffrey Woodhouse

Michael T Ross

Allan O Cruz

Michelle Gill

David V MacDonnell, Ii

Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects

Modifying design layer of integrated circuit (IC)

Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.

Trimming of dummy fill shapes holes to affect near-neighbor dummy fill shapes with built-in optical proximity corrections for semiconductor applications

Variation of a parameter of interest is reduced over a field of interest in, for example, an object design, such as a circuit design. The field of interest is divided into tiles. A parameter value is found for each tile and for a group of tiles around each tile. Using these values, variation of the parameter is determined. An adjusted value of the parameter for each tile is determined taking limits into account, iterating until variation is below a threshold value. Parameter uniformity is improved in some applications by over 30% with runtime reduced by an order of magnitude.

Parameter variation improvement

Disclosed are integrated circuit design systems and methods, wherein selected functional library elements are placed in a layout to meet product specifications and selected hybrid fill-placeable library elements are placed in that same layout to meet at least one feature density rule. Each hybrid fill-placeable library element comprises fill shapes corresponding to specific features subject to a density rule and a marker shape that provides an instruction to ignore any density rule violations within that element for purposes of design rule checking. Placement of the hybrid fill-placeable library elements is performed to balance out density rule violations in functional library elements elsewhere in the layout, thereby avoiding the need for post-processing of the completed IC design to add fill shapes. Optionally, each hybrid fill-placeable library element comprises different fill shapes at different levels and corresponding to different features so that it can be employed to meet multiple different density rules.

Method and system allowing for semiconductor design rule optimization

A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections

Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications

A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer

Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.

Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes

A method, system and program product for replacing isotropic hole shapes in a wiring layout with non-equiaxial hole shapes that are arranged in a direction of current flow, which increases current flow along the wire's longitudinal axis while decreasing current flow along the wire's transverse axis. One aspect of the invention includes a method including determining a direction of electrical current flow in a portion of a wiring layout; and placing at least one non-equiaxial hole shape within the portion of the wiring layout, wherein the non-equiaxial hole shape is arranged in the direction of electrical current flow. The invention accommodates the limitations of copper CMP within an automated tool without sacrificing the efficiency of a hand-tuned layout. The invention also includes a semiconductor device including at least one non-equiaxial hole shape.

Current-aligned auto-generated non-equiaxial hole shape for wiring

A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.

SOI (silicon on insulator) substrate improvements

A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.

Formation of masks/reticles having dummy features

Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous metal fill structure is limited up to three vertically adjoining metal interconnect levels, thereby limiting the capacitance of each contiguous metal fill structure. Capacitive coupling between the contiguous metal fill structures and the metal interconnect structures is minimized due to the fragmented structure of contiguous metal fill structures.

Metal fill structures for reducing parasitic capacitance

Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Method and structures for improving substrate loss and linearity in SOI substrates

A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias.

System and method of automated wire and via layout optimization description

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Underhill, VT, United States of America

Howard Smith Landis