The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2011

Filed:

Aug. 18, 2006
Applicants:

Bette L. Bergman Reuter, Essex Junction, VT (US);

Howard S. Landis, Underhill, VT (US);

Anthony K. Stamper, Williston, VT (US);

Jeanne-tania Sucharitaves, Williston, VT (US);

Inventors:

Bette L. Bergman Reuter, Essex Junction, VT (US);

Howard S. Landis, Underhill, VT (US);

Anthony K. Stamper, Williston, VT (US);

Jeanne-Tania Sucharitaves, Williston, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias.


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