IDiyas

For the Inventor, By the Inventor

Williston, VT, United States of America

Jeanne-Tania Sucharitaves

USPTO Granted Patents = 12

Average Co-Inventor Count = 3.2

ph-index = 4

Forward Citations = 33(Granted Patents)


Location History:

  • Essex Junction, VT (US) (2010)
  • Williston, VT (US) (2007 - 2012)
  • Bangkok, TH (2011 - 2013)

Company Filing History:

goldMedal12 out of 164,108 
 
International Business Machines Corporation
 patents

Years Active: 2007-2013

Loading Chart...
12 patents (USPTO):
1. 8438509 - Automated generation of oxide pillar slot shapes in silicon-on-insulator formation technology (2013-05-07),
2. 8299775 - Current-aligned auto-generated non-equiaxial hole shape for wiring (2012-10-30),
3. 8176447 - Formation of masks/reticles having dummy features (2012-05-08),
4. 8006211 - IC chip and design structure including stitched circuitry region boundary identification (2011-08-23),
5. 7958482 - Stitched circuitry region boundary identification for stitched IC chip layout (2011-06-07),
6. 7930667 - System and method of automated wire and via layout optimization description (2011-04-19),
7. 7861208 - Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks (2010-12-28),
8. 7858269 - Structure and method for sub-resolution dummy clear shapes for improved gate dimensional control (2010-12-28),
9. 7739648 - Formation of masks/reticles having dummy features (2010-06-15),
10. 7739632 - System and method of automated wire and via layout optimization description (2010-06-15),
11. 7709300 - Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks (2010-05-04),
12. 7250363 - Aligned dummy metal fill and hole shapes (2007-07-31),

Title: Innovator Spotlight: Jeanne-Tania Sucharitaves

Introduction:

Meet Jeanne-Tania Sucharitaves, a prolific inventor based in Williston, VT, with an impressive portfolio of 12 patents. His groundbreaking work in automated silicon-on-insulator formation technology and wiring layout optimization has cemented his reputation as a visionary in the field.

Latest Patents:

1. Automated Generation of Oxide Pillar Slot Shapes in Silicon-on-Insulator Formation Technology: This patent details a method for automating the generation of oxide pillar (PX) slot shapes within silicon-on-insulator (SOI) structures. By streamlining the process of creating PX slot shapes and correcting location errors, this innovation revolutionizes SOI fabrication.

2. Current-Aligned Auto-Generated Non-Equiaxial Hole Shape for Wiring: This patent introduces a method for replacing isotropic hole shapes in wiring layouts with non-equiaxial shapes aligned with the direction of current flow. By enhancing current flow efficiency, this invention optimizes wiring layouts for improved performance.

Career Highlights:

Jeanne-Tania Sucharitaves is a key figure at the renowned International Business Machines Corporation (IBM) where his innovative spirit has thrived. His contributions to SOI technology and wiring layout optimization have reshaped the industry's approach to semiconductor device fabrication.

Collaborations:

In his pioneering work, Jeanne-Tania Sucharitaves has collaborated closely with esteemed colleagues such as Howard Smith Landis and Amit Kumar. Together, they have pushed the boundaries of innovation in semiconductor technology and brought cutting-edge solutions to the forefront.

Conclusion:

In conclusion, Jeanne-Tania Sucharitaves stands as a trailblazing inventor whose relentless pursuit of excellence has led to groundbreaking advancements in silicon-on-insulator technology and wiring layout optimization. His collaborative spirit and innovative mindset continue to inspire progress in the field of semiconductor device fabrication.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…