The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Apr. 30, 2008
Robert K. Leidy, Burlington, VT (US);
Kevin N. Ogg, Burlington, VT (US);
Richard J. Rassel, Essex Jct, VT (US);
Jeanne-tania Sucharitaves, Bangkok, TH;
Robert K. Leidy, Burlington, VT (US);
Kevin N. Ogg, Burlington, VT (US);
Richard J. Rassel, Essex Jct, VT (US);
Jeanne-Tania Sucharitaves, Bangkok, TH;
International Business Machines Corporation, Armonk, NY (US);
Abstract
Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.