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For the Inventor, By the Inventor

Hopewell Junction, NY, United States of America

Stuart A Sieg

USPTO Granted Patents = 67 

Average Co-Inventor Count = 4.6

ph-index = 7

Forward Citations = 174(Granted Patents)

Forward Citations (Not Self Cited) = 153(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Hopewell Junction, NY (US) (2012 - 2013)
  • Albany, NY (US) (2014 - 2024)

Company Filing History:

goldMedal61 out of 164,221 
 
International Business Machines Corporation
 patents
silverMedal4 out of 1,857 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
bronzeMedal2 out of 5,671 
 
Globalfoundries Inc.
 patents

Years Active: 2012-2025

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Areas of Expertise:
Buried Power Rail
Fin Field Effect Transistor
Vertical Transistors
Self-Aligned Double Patterning
Tight-Pitch Line Formation
Selective Source/Drain Recess
Tunable Hardmask
Material Planarization
EUV Lithography
Gate Length Control
Strained FinFET
Vertical Transport Devices
67 patents (USPTO):Explore Patents
1. 12444653 - Buried power rail at tight cell-to-cell space (2025-10-14),
2. 12406930 - Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure (2025-09-02),
3. 12324236 - Bottom contact for stacked GAA FET (2025-06-03),
4. 12268026 - High aspect ratio contact structure with multiple metal stacks (2025-04-01),
5. 12148617 - Structure and method to pattern pitch lines (2024-11-19),
6. 12080559 - Using a same mask for direct print and self-aligned double patterning of nanosheets (2024-09-03),
7. 11990412 - Buried power rails located in a base layer including first, second, and third etch stop layers (2024-05-21),
8. 11610780 - Alternating hardmasks for tight-pitch line formation (2023-03-21),
9. 11257681 - Using a same mask for direct print and self-aligned double patterning of nanosheets (2022-02-22),
10. 11205723 - Selective source/drain recess for improved performance, isolation, and scaling (2021-12-21),
11. 11183389 - Fin field effect transistor devices with self-aligned gates (2021-11-23),
12. 11171002 - Alternating hardmasks for tight-pitch line formation (2021-11-09),
13. 11121024 - Tunable hardmask for overlayer metrology contrast (2021-09-14),
14. 11031248 - Alternating hardmasks for tight-pitch line formation (2021-06-08),
15. 10985025 - Fin cut profile using fin base liner (2021-04-20),

Title: The Innovations of Stuart A Sieg: Pioneering Technologies in Semiconductor Industry

Introduction: Stuart A Sieg, a prolific inventor based in Hopewell Junction, NY, has made significant contributions to the field of semiconductor technology with an impressive portfolio of 61 patents.

Latest Patents: Among his recent patents, one of the groundbreaking ideas involves buried power rails located in a base layer with multiple etch stop layers. Another innovative concept includes alternating hardmasks for tight-pitch line formation, revolutionizing the method for forming fins in semiconductor manufacturing.

Career Highlights: Stuart A Sieg has excelled in his career with notable tenures at renowned companies such as IBM and Tessera, Inc. His expertise and innovative spirit have played a pivotal role in advancing semiconductor technologies.

Collaborations: Throughout his career, Stuart A Sieg has collaborated closely with esteemed colleagues like Fee Li Lie and Sivananda K Kanakasabapathy, fostering a culture of innovation and knowledge sharing within the semiconductor industry.

Conclusion: Stuart A Sieg's relentless pursuit of innovation and his remarkable patent portfolio underscore his status as a trailblazer in the semiconductor domain. His contributions continue to shape the future of technology, making him a standout figure in the world of inventions and patents.

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