The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Jun. 24, 2022
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Su Chen Fan, Cohoes, NY (US);
Stuart Sieg, Albany, NY (US);
Xuan Liu, Clifton Park, NY (US);
Junli Wang, Slingerlands, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/43 (2025.01); H10D 30/6211 (2025.01); H10D 30/6735 (2025.01);
Abstract
A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.
Fan, Su. (2026). Common self aligned gate contact for stacked transistor structures (U.S. Patent No. 12581702). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12581702
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile