Shashank C Deshmukh

This inventor holds 24 USPTO granted patents and 2 published patent applications, primarily in Plasma Etching Technology. Top assignees: Applied Materials, Inc., Lam Research Corporation. Active years: 1998-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shashank C Deshmukh. Retrieved from https://idiyas.com/inventor/shashank-c-deshmukh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24 (Patent Applications = 2)

% Patents Active = 54.2

Average Co-Inventor Count = 4.1

ph-index = 10

Forward Citations = 392(Granted Patents)

Location History:

Sunnyvale, CA (US) (1998 - 2002)
San Jose, CA (US) (2003 - 2014)
San Ramon, CA (US) (2012 - 2019)

Company Filing History:

21 out of 14,433

Applied Materials, Inc.

patents

3 out of 3,940

Lam Research Corporation

patents

Years Active: 1998-2019

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Areas of Expertise:

Plasma Etching

Dielectric Materials

Semiconductor Structures

High-K Dielectrics

CMOS Logic Gates

Flash Memory

Temperature Control

Etch Selectivity

Surface Contamination

Reaction Gas

Silicon Trench

Hardmask

24 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10361091 - Porous low-k dielectric etch (2019-07-23),

2. 9396961 - Integrated etch/clean for dielectric etch applications (2016-07-19),

3. 9079228 - Methodology for cleaning of surface metal contamination from an upper electrode used in a plasma chamber (2015-07-14),

4. 8956500 - Methods to eliminate 'M-shape' etch rate profile in inductively coupled plasma reactor (2015-02-17),

5. 8722547 - Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries (2014-05-13),

6. 8501626 - Methods for high temperature etching a high-K material gate structure (2013-08-06),

7. 8133817 - Shallow trench isolation etch process (2012-03-13),

8. 7910488 - Alternative method for advanced CMOS logic gate etch applications (2011-03-22),

9. 7780862 - Device and method for etching flash memory gate stacks comprising high-k dielectric (2010-08-24),

10. 7771606 - Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures (2010-08-10),

11. 7754610 - Process for etching tungsten silicide overlying polysilicon particularly in a flash memory (2010-07-13),

12. 7737042 - Pulsed-plasma system for etching semiconductor structures (2010-06-15),

13. 7718538 - Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates (2010-05-18),

14. 7504338 - Method of pattern etching a silicon-containing hard mask (2009-03-17),

15. 7368392 - Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode (2008-05-06),

Title: The Innovative Journey of Shashank C Deshmukh

Introduction: Shashank C Deshmukh, a talented inventor based in San Jose, CA, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents: Shashank C Deshmukh holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his diverse expertise and forward-thinking approach.

Career Highlights: Throughout his career, Shashank C Deshmukh has worked with leading tech companies, spearheading research and development projects that have led to the creation of cutting-edge products and solutions.

Collaborations: Shashank C Deshmukh has collaborated with top researchers, engineers, and scientists from around the world, fostering a culture of innovation and excellence in all his projects.

Conclusion: Shashank C Deshmukh's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

2 patents pending: