Applied Materials, Inc.

Lam Research Corporation

Shashank C Deshmukh

Meihua Shen

Kyeong-Tae Lee

Wei Liu

Jeffrey D Chinn

Tae Won Kim

Ajay Kumar

Valentin Nikolov Todorow

Alexander Miller Paterson

Rolf A Guenther

Nicolas Gani

Weinan Jiang

Eric A Hudson

Thorsten B Lill

Anisul Haque Khan

Jinhan Choi

Hiroki Sasano

Radhika C Mani

Mark Wiltse

Yan Du

Bruce Minaee

Hong Shih

Reza Arghavani

Samantha SiamHwa Tan

Michael D Willwerth

Xikun Wang

David S Mui

Armen Avoyan

Gerardo Delgadino

Dragan Valentin Podlesnik

Ralph M Wadensweiler

David Palagashvili

Sunil Srinivasan

Tom A Kamp

Valentin N Todorov

David S L Mui

Stephen Yuen

David Z Carman

Jeff Chinn

Yung-Hee Yvette Lee

Prabhakara Gopaladasu

Sang In Yi

Daehee Weon

Jitske Trevor

Chia-Chun Wang

Zihao Ouyang

Yohei Kawase

Bi Jang

Sonny Li

Jae Bum Yu

Marco Mombelli

Brian Duda

Eiichi Matsusue

Anh-Kiet Quang Phan

Jong I Shin

Barrett Finch

A method for etching features into a porous low-k dielectric etch layer is provided. A plurality of cycles is performed in a plasma processing chamber. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon and/or hydrofluorocarbon gas, creating a plasma in the plasma processing chamber using the deposition gas, depositing a fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising a noble gas and a carbon etching additive, creating a plasma in the plasma processing chamber using the activation gas, providing an activation bias in the plasma processing chamber, wherein the activation bias causes the etching of the low-k dielectric layer, with consumption of the fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the activation gas.

Porous low-k dielectric etch

The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Integrated etch/clean for dielectric etch applications

A method for cleaning metallic contaminants from an upper electrode used in a plasma chamber. The method comprises a step of soaking the upper electrode in a cleaning solution of concentrated ammonium hydroxide, hydrogen peroxide and water. The cleaning solution is free of hydrofluoric acid and hydrochloric acid. The method further comprises an optional step of soaking the upper electrode in dilute nitric acid and rinsing the cleaned upper electrode.

Methodology for cleaning of surface metal contamination from an upper electrode used in a plasma chamber

An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.

Methods to eliminate 'M-shape' etch rate profile in inductively coupled plasma reactor

Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl, setting the temperature of the wafer to be between 100&#xb0; C. and 350&#xb0; C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl, setting the temperature of the wafer to be between 20&#xb0; C. and 200&#xb0; C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl, setting the temperature of the wafer to be between 20&#xb0; C. and 200&#xb0; C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries

Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Methods for high temperature etching a high-K material gate structure

Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.

Shallow trench isolation etch process

Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.

Alternative method for advanced CMOS logic gate etch applications

In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.

Device and method for etching flash memory gate stacks comprising high-k dielectric

A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.

Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures

A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NFand Cl. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiClmay be added for additional selectivity.

Process for etching tungsten silicide overlying polysilicon particularly in a flash memory

A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.

Pulsed-plasma system for etching semiconductor structures

A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.

Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates

Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CFto CHF, where the volumetric ratio of CFto CHFis within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1.5:1 or better. The method also provides an etch profile sidewall angle ranging from 88&#xb0; to 92&#xb0; between said etched silicon-containing dielectric layer and an underlying horizontal layer. in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.

Method of pattern etching a silicon-containing hard mask

A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.

Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode

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San Jose, CA, United States of America

Shashank C Deshmukh