The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2010

Filed:

Feb. 21, 2007
Applicants:

Tae Won Kim, San Jose, CA (US);

Kyeong-tae Lee, San Jose, CA (US);

Alexander Paterson, San Jose, CA (US);

Valentin N. Todorov, Palo Alto, CA (US);

Shashank C. Deshmukh, San Jose, CA (US);

Inventors:

Tae Won Kim, San Jose, CA (US);

Kyeong-Tae Lee, San Jose, CA (US);

Alexander Paterson, San Jose, CA (US);

Valentin N. Todorov, Palo Alto, CA (US);

Shashank C. Deshmukh, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.


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