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For the Inventor, By the Inventor

Bangkok, Thailand

Saravuth Sirinorakul

This inventor holds 76 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Packaging (CPC class H01L). Top assignees: Utac Thai Limited, Utac Headquarters Pte. Ltd., Ns Electronics Bangkok (1993) Ltd.. Active years: 2005-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Saravuth Sirinorakul. Retrieved from https://idiyas.com/inventor/saravuth-sirinorakul

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 76 

% Patents Active = 98.7

Average Co-Inventor Count = 2.0

ph-index = 10

Forward Citations = 380(Granted Patents)

Forward Citations (Not Self Cited) = 314(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Bangna, TH (2007 - 2008)
  • Bagkok, TH (2017)
  • Bangkok, TH (2005 - 2024)

Company Filing History:

goldMedal40 out of 50 
 
Utac Thai Limited
 patents
silverMedal29 out of 79 
 
Utac Headquarters Pte. Ltd.
 patents
bronzeMedal5 out of 5 
 
Ns Electronics Bangkok (1993) Ltd.
 patents
4. 1 out of 48 
 
United Test and Assembly Center Limited
 patents
5. 1 out of 1 
 
Utac Dongguan Ltd.
 patent

Years Active: 2005-2024

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Areas of Expertise:
Semiconductor Packages
Integrated Shielding
Stacked Dies
Protective Layer
Cavity Wall Structure
Heat Spreader
Plated Metal Shielding
Leadframes
Molding Routing Layers
Flip Chip Package
Post-Mold Processing
Bond Wire Stabilization
76 patents (USPTO):Explore Patents
1. 11901308 - Semiconductor packages with integrated shielding (2024-02-13),
2. 11804416 - Semiconductor device and method of forming protective layer around cavity of semiconductor die (2023-10-31),
3. 11227818 - Stacked dies electrically connected to a package substrate by lead terminals (2022-01-18),
4. 11139233 - Cavity wall structure for semiconductor packaging (2021-10-05),
5. 10734247 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2020-08-04),
6. 10707161 - Cavity wall structure for semiconductor packaging (2020-07-07),
7. 10658277 - Semiconductor package with a heat spreader and method of manufacturing thereof (2020-05-19),
8. 10600741 - Semiconductor package with plated metal shielding and a method thereof (2020-03-24),
9. 10586771 - Conductive shield for semiconductor package (2020-03-10),
10. 10515878 - Semiconductor package with partial plating on contact side surfaces (2019-12-24),
11. 10361146 - Semiconductor package with multiple stacked leadframes and a method of manufacturing the same (2019-07-23),
12. 10325782 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2019-06-18),
13. 10276477 - Semiconductor package with multiple stacked leadframes and a method of manufacturing the same (2019-04-30),
14. 10269686 - Method of improving adhesion between molding compounds and an apparatus thereof (2019-04-23),
15. 10242953 - Semiconductor package with plated metal shielding and a method thereof (2019-03-26),

Title: Saravuth Sirinorakul: A Driving Force in Semiconductor Innovation

Introduction:

Saravuth Sirinorakul, a resident of Bangkok, Thailand, is a prolific inventor with an impressive track record of 75 patents. His expertise lies in the field of semiconductor devices, where he has made significant advancements in protective layer formation and stacked die technology. Let us explore the latest patents, career highlights, and collaborations that have shaped Sirinorakul's contribution to the field of innovations and patents.

Latest Patents:

One of Sirinorakul's recent patents is for a semiconductor device with a unique method of forming a protective layer around the cavity of a semiconductor die. This innovation ensures that the cavity remains unobstructed by encapsulant, allowing for unimpeded access to the sensor within the semiconductor die. This technological breakthrough enhances the reliability of sensor detection and measurement.

Another notable patent relates to stacked dies in a package substrate. Sirinorakul's invention employs a conductive gang with gang legs that electrically connect a second component stacked above a first die to the package substrate. This approach enables efficient electrical coupling and enhances the overall performance of the stacked package.

Career Highlights:

Sirinorakul's career has been marked by his association with renowned companies in the semiconductor industry. He has worked with Utac Thai Limited, a prominent player in semiconductor assembly and test services, and Utac Headquarters Pte Ltd. These associations have enabled him to contribute his expertise to cutting-edge semiconductor projects and pave the way for technological advancements.

Collaborations:

Sirinorakul has had the privilege of collaborating with esteemed individuals in his field. Among his notable coworkers are Somchai Nondhasitthichai and Suebphong Yenrudee. Their collective efforts have fostered an environment of innovation and have contributed to the successful realization of numerous patents and inventions.

Conclusion:

Saravuth Sirinorakul's impressive portfolio of 75 patents and his exceptional work in the field of semiconductor devices demonstrate his invaluable contributions to the industry. His latest patents showcase his ingenuity in protective layer formation and stacked die technology. Through his collaborations and associations with renowned companies, Sirinorakul continues to be a driving force in semiconductor innovation. As he forges ahead, the industry eagerly awaits the next wave of inventions and breakthroughs that will shape the future of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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