The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

May. 22, 2017
Applicant:

Utac Headquarters Pte. Ltd., Singapore, SG;

Inventors:

Somchai Nondhasitthichai, Bangkok, TH;

Saravuth Sirinorakul, Bangkok, TH;

Woraya Benjasukul, Bangkok, TH;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49541 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/495 (2013.01); H01L 23/49503 (2013.01);
Abstract

Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.


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