Utac Thai Limited

Utac Headquarters Pte. Ltd.

Ns Electronics Bangkok (1993) Ltd.

United Test and Assembly Center Limited

Utac Dongguan Ltd.

Saravuth Sirinorakul

Somchai Nondhasitthichai

Suebphong Yenrudee

Kasemsan Kongthaworn

Yee Heong Chua

Vorajit Suwannaset

Roel Adeva Robles

Albert Loh

Arlene V Layson

Antonio Bambalan Dimaano, Jr

Hua Hong Tan

Kriangsak Sae Le

Keith M Edwards

Woraya Benjavasukul

Siriwanna Ounkaew

Paweena Phatto

Sant Hongsongkiat

Sitta Jewjaitham

Chatchawan Injan

Somsak Phukronghin

Woraya Benjasukul

Kok Chuen Lock

Preecha Joymak

Wilson Poh Leng Ong

Chanapat Kongpoung

Somchai Nondhasittichai

Il Kwon Shim

Rui Huang

Serafin Padilla Pedron, Jr

Thanawat Jaengkrajarng

Eakkasit Dumsong

Natawat Kasikornrungroj

Edward Then

Wing Keung Lam

Somohal Nondhasitthichai

Thada Suriyanun

Kawin Saiubol

Somchai Nondhasitthichail

Wasu Aingkaew

Nataporn Charusabha

The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.

Semiconductor packages with integrated shielding

A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.

Semiconductor device and method of forming protective layer around cavity of semiconductor die

An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.

Stacked dies electrically connected to a package substrate by lead terminals

A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

Cavity wall structure for semiconductor packaging

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

Semiconductor package with multiple molding routing layers and a method of manufacturing the same

An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.

Semiconductor package with a heat spreader and method of manufacturing thereof

Methods of manufacturing semiconductor packages with metal-plated shields include roughening surfaces of a molding compound by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. In one embodiment, the method includes obtaining a molded array including a plurality of dies coupled to a substrate and a molding compound encapsulating the plurality of dies, coating all exposed surfaces of the molding compound with an adhesion promoter material, heating the molded array with an adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film, and etching away the baked film, resulting in the molding compound having the roughened surfaces. Preferably, the method also includes depositing a catalyst material on the roughened surfaces before a metal layer is coated on the roughened surfaces to speed up the time for the metal layer to adhere to the roughened surfaces.

Semiconductor package with plated metal shielding and a method thereof

A conductive polymer shielding layer covering insulating layer formed on an integrated-circuit die is provided and a method thereof. The method comprises die attaching, wire bonding, back etching, insulation molding, partial cutting, conductive material/polymer coating, and singulation.

Conductive shield for semiconductor package

Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.

Semiconductor package with partial plating on contact side surfaces

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

Semiconductor package with multiple stacked leadframes and a method of manufacturing the same

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

Embodiments of the present invention relate to a semiconductor package that includes a locking feature. The locking feature is provided by an unnatural surface roughness of a first molding compound to increase adhesion with a second molding compound. Surfaces of first molding compound are roughened by an abrasion process such that the surfaces are rougher than a natural surface roughness. The roughened surfaces of the first molding compound provide better adhesion of the second molding compound to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness).

Method of improving adhesion between molding compounds and an apparatus thereof

Embodiments of the present invention are directed to a semiconductor package with full plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface and a second surface that is at one of the side surfaces. The first surface and the second surface of each of the contacts are continuously plated. Portions of an internal plating layer are exposed along the side surfaces of the semiconductor package. The semiconductor package has a molding compound at least partially encapsulating the contacts, wherein the surface of a first part of the molding compound and the surface of a second part of the molding compound have different surface texture.

Semiconductor package with full plating on contact side surfaces and methods thereof

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Bangkok, Thailand

Saravuth Sirinorakul