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For the Inventor, By the Inventor

Los Altos, CA, United States of America

Milind S Bhagavat

This inventor holds 65 USPTO granted patents and 8 published patent applications and 4 EPO patents, primarily in 3D Integrated Circuits (CPC class H01L). Top assignees: Advanced Micro Devices Corporation, Apple Inc., Memc Electronic Materials, Inc.. Active years: 2003-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Milind S Bhagavat. Retrieved from https://idiyas.com/inventor/milind-s-bhagavat

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 65 

% Patents Active = 93.8

 

Average Co-Inventor Count = 3.1

ph-index = 9

Forward Citations = 345(Granted Patents)

Forward Citations (Not Self Cited) = 300(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • St. Louis, MO (US) (2003)
  • Medford, MA (US) (2009 - 2013)
  • Fremont, CA (US) (2012 - 2017)
  • Mountain View, CA (US) (2020)
  • Livermore, CA (US) (2021)
  • Cupertino, CA (US) (2016 - 2023)
  • Los Altos, CA (US) (2018 - 2023)
  • Broomfield, CO (US) (2021 - 2023)
  • Santa Clara, CA (US) (2023)

Company Filing History:

goldMedal44 out of 13,175 
 
Advanced Micro Devices Corporation
 patents
silverMedal8 out of 43,632 
 
Apple Inc.
 patents
bronzeMedal6 out of 347 
 
Memc Electronic Materials, Inc.
 patents
4. 4 out of 11,124 
 
Broadcom Corporation
 patents
5. 3 out of 3,703 
 
Analog Devices,inc.
 patents
6. 1 out of 1,121 
 
Ati Technologies Ulc
 patents
where one patent can have more than one assignee

Years Active: 2003-2025

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Areas of Expertise:
3D Stacked Dies
Thermal Management
Semiconductor Packaging
Chiplet Connectivity
Hybrid Bonding
Multi-Chip Packages
Optical Encoders
High Bandwidth Crosslinks
Integrated Voltage Regulators
Die Stacking
Compact Passive Components
Molded Chip Packages
65 patents (USPTO):Explore Patents
1. 12394683 - Molded semiconductor chip package with stair-step molding layer (2025-08-19),
2. 12266585 - Arrangement and thermal management of 3D stacked dies (2025-04-01),
3. 12249519 - Molded chip package with anchor structures (2025-03-11),
4. 12183675 - Fan-out packages with warpage resistance (2024-12-31),
5. 12170263 - Fabricating active-bridge-coupled GPU chiplets (2024-12-17),
6. 11855061 - Offset-aligned three-dimensional integrated circuit (2023-12-26),
7. 11841803 - GPU chiplets using high bandwidth crosslinks (2023-12-12),
8. 11837588 - Circuit board with compact passive component arrangement (2023-12-05),
9. 11810891 - Bond pads for low temperature hybrid bonding (2023-11-07),
10. 11804479 - Scheme for enabling die reuse in 3D stacked products (2023-10-31),
11. 11742301 - Fan-out package with reinforcing rivets (2023-08-29),
12. 11715691 - Integrated circuit package with integrated voltage regulator (2023-08-01),
13. 11676924 - Semiconductor chip with reduced pitch conductive pillars (2023-06-13),
14. 11670624 - Integrated circuit module with integrated discrete devices (2023-06-06),
15. 11658123 - Hybrid bridged fanout chiplet connectivity (2023-05-23),

Title: Milind S Bhagavat: An Innovator in Semiconductor Technology

Introduction

Milind S Bhagavat, based in Los Altos, California, is a distinguished inventor with an impressive portfolio of 61 patents. His contributions to the semiconductor industry reflect a deep understanding of complex electronic systems and innovative design principles.

Latest Patents

Among his latest innovations are two notable patents. The first is focused on fan-out packages with warpage resistance. This invention discusses various molded fan-out semiconductor chip devices, featuring a first molding layer with internal conductor structures, a redistribution layer (RDL) structure, and a semiconductor chip that is effectively encapsulated by a second molding layer. This design aims to enhance durability and performance in chip packaging.

The second patent addresses an offset-aligned three-dimensional integrated circuit. This circuit comprises a first die structure operating at different power densities in its regions. It also involves a second die structure, stacked and aligned with the first region of the first die structure, showcasing sophisticated engineering that optimizes space and power efficiency in multi-layer chip designs.

Career Highlights

Milind has made significant strides in his career, working with prestigious companies such as Advanced Micro Devices Corporation and Apple Inc. His experience in these leading organizations has contributed immensely to his innovative capabilities and understanding of cutting-edge semiconductor technologies.

Collaborations

Throughout his career, Milind has collaborated with talented individuals such as Rahul Kumar Agarwal and Brett P Wilkerson. These partnerships have further fueled his inventive spirit, leading to advancements in semiconductor design and manufacturing processes.

Conclusion

Milind S Bhagavat stands out as a prominent figure in semiconductor innovation. His numerous patents exemplify his commitment to developing technologies that address the challenges of modern electronics. Through his work, he continues to push the boundaries of what is possible in the field, influencing the future of integrated circuits and semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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