The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Mar. 02, 2021
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Priyal Shah, Santa Clara, CA (US);

Milind S. Bhagavat, Broomfield, CO (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/80 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 2224/0384 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05118 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/0614 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/8034 (2013.01); H01L 2224/8089 (2013.01); H01L 2224/80801 (2013.01); H01L 2224/80906 (2013.01);
Abstract

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.


Find Patent Forward Citations

Shah, Priyal. (2023). Bond pads for low temperature hybrid bonding (U.S. Patent No. 11810891). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11810891

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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