The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2025
Filed:
Mar. 18, 2020
Applicant:
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Inventors:
Priyal Shah, San Jose, CA (US);
Rahul Agarwal, Livermore, CA (US);
Milind S. Bhagavat, Broomfield, CO (US);
Chia-Hao Cheng, Hsinchu, TW;
Assignee:
ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/304 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 21/3043 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 23/3121 (2013.01); H01L 24/96 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01);
Abstract
Various molded semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a routing substrate and a semiconductor chip mounted on and electrically connected to the routing substrate. The semiconductor chip has plural side surfaces. A molding layer at least partially encases the semiconductor chip. The molding layer has a tread and a riser, the riser abutting at least some of the side surfaces.