The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Dec. 14, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Milind S. Bhagavat, Cupertino, CA (US);

Rahul Agarwal, San Francisco, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01); H01L 23/3142 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 28/40 (2013.01);
Abstract

An integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, a row of discrete devices disposed laterally with respect to the integrated circuit die, and encapsulant mechanically coupling the redistribution layer, integrated circuit die, and the row of discrete devices. In at least one embodiment, the row of discrete devices is a row of decoupling capacitors disposed proximate to the integrated circuit die and coupled to the integrated circuit die and a power distribution network. In at least one embodiment, a second integrated circuit die is disposed above the redistribution layer and disposed laterally with respect to the integrated circuit die and the row of discrete devices. The second integrated circuit die is mechanically coupled to the redistribution layer, integrated circuit die, and the row of discrete devices and is partially surrounded by the row of discrete devices.


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