Singapore, Singapore

Jeffrey David Punzalan

This inventor holds 70 USPTO granted patents and 1 published patent application, primarily in Integrated Circuit Packaging (CPC class H01L). Top assignees: Stats Chippac Pte. Ltd., St Assembly Test Services Inc.. Active years: 2003-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeffrey David Punzalan. Retrieved from https://idiyas.com/inventor/jeffrey-david-punzalan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 70 

% Patents Active = 97.1

Average Co-Inventor Count = 3.9

ph-index = 11

Forward Citations = 426(Granted Patents)

Forward Citations (Not Self Cited) = 404(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Singapore, SA (2012)
  • Singapore, SG (2003 - 2018)

Company Filing History:


Years Active: 2003-2018

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Areas of Expertise:
Integrated Circuit
Packaging System
Wafer Level Package
Substrate
Interposer Structure
Non-Leaded Package
Bump Interconnection
Leadfinger
Thermal Management
Flip-Chip
Die Support
Encapsulation
70 patents (USPTO):Explore Patents

Title: Jeffrey David Punzalan: Innovator in Integrated Circuit Packaging

Introduction

Jeffrey David Punzalan is a prominent inventor based in Singapore, known for his significant contributions to the field of integrated circuit packaging. With an impressive portfolio of 69 patents, he has demonstrated an exceptional ability to innovate and enhance technologies critical to modern electronics.

Latest Patents

Punzalan's latest innovations include the following patents:

1. **Integrated Circuit Packaging System with Substrate and Method of Manufacture Thereof** - This patent describes a comprehensive integrated circuit packaging system, which features a substrate with a first trace layer, an encapsulation on the first trace layer, and a second trace layer on top of that. This design incorporates a rough texture characteristic of the removal of a conductive carrier coating, allowing for efficient attachment of an integrated circuit die to the substrate.

2. **Integrated Circuit Packaging System with Interposer Structure and Method of Manufacture Thereof** - This patent outlines a system that includes a pillar with conductive buildup attached to it, encapsulated by a molded body. The pillar extending out of the molded body improves the efficiency and performance of integrated circuit packaging designs.

Career Highlights

Throughout his career, Punzalan has worked with notable companies such as Stats Chippac Pte. Ltd. and St Assembly Test Services Inc. His experience in these organizations has significantly contributed to his expertise in integrated circuit technology and patent development.

Collaborations

Jeffrey has collaborated with remarkable individuals in the field, including his coworkers Zigmund Ramirez Camacho and Henry Descaizo Bathan. These collaborations have likely fostered a creative environment that spurred further innovations and advancements.

Conclusion

Jeffrey David Punzalan has established himself as a leading inventor in integrated circuit packaging with a robust portfolio of patents. His work not only advances technology within the electronics industry but also sets a foundation for future innovations. His contributions are a testament to the importance of creativity and collaboration in the pursuit of technological advancement.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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