The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Jun. 26, 2014
Applicants:

Emmanuel Espiritu, Singapore, SG;

Allan Pumatong Ilagan, Singapore, SG;

Jeffrey David Punzalan, Singapore, SG;

Inventors:

Emmanuel Espiritu, Singapore, SG;

Allan Pumatong Ilagan, Singapore, SG;

Jeffrey David Punzalan, Singapore, SG;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 23/12 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01); H01L 23/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 23/12 (2013.01); H01L 23/28 (2013.01); H01L 23/5384 (2013.01); H01L 24/81 (2013.01);
Abstract

An integrated circuit packaging system and method of manufacture thereof includes: discrete components coupled to a top trace; vias attached to the top trace separated from the discrete components; a dielectric layer on the top trace, the discrete components, and the vias, includes a component surface formed above the discrete components, with the top trace coplanar with the dielectric layer; and system interconnects coupled to the vias for electrically connecting the top trace, the discrete components, or a combination thereof to the system interconnects.


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