The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Aug. 02, 2016
Applicant:

Stats Chippac Pte. Ltd., Singapore, SG;

Inventors:

Dao Nguyen Phu Cuong, Singapore, SG;

Bartholomew Liao Chung Foh, Singapore, SG;

Byung Tai Do, Singapore, SG;

Kyung Moon Kim, Seongnam, KR;

Jeffrey David Punzalan, Singapore, SG;

SeungYong Chai, Hwaseong-si, KR;

Soo Won Lee, Yongin-si, KR;

Kwok Keung Szeto, Singapore, SG;

KyungOe Kim, Daejeon, KR;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 21/76877 (2013.01); H01L 23/3192 (2013.01); H01L 23/5384 (2013.01);
Abstract

An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.


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