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For the Inventor, By the Inventor

Changhua, Taiwan

Hsien-Ming Lee

This inventor holds 62 USPTO granted patents and 11 published patent applications, primarily in Semiconductor Devices (CPC class H01L). Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2005-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsien-Ming Lee. Retrieved from https://idiyas.com/inventor/hsien-ming-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 62 

% Patents Active = 88.7

Average Co-Inventor Count = 5.0

ph-index = 5

Forward Citations = 118(Granted Patents)

Forward Citations (Not Self Cited) = 102(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Datsuen Shiang, TW (2020 - 2021)
  • Changhua, TW (2005 - 2024)

Company Filing History:

goldMedal62 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2005-2026

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Areas of Expertise:
Metal Gate Structure
Transistor Manufacturing
Semiconductor Device
Capping Layers
FinFET Structures
Threshold Voltage Tuning
In-Situ Etching
Void Elimination
Work-Function Materials
High-Aspect Ratio Trenches
Low-Resistivity Conductive Layer
Hybrid Capping Layer
62 patents (USPTO):Explore Patents
1. 12733199 - Gate resistance reduction through low-resistivity conductive layer (2026-09-08),
2. 12431356 - Metal gate structure and method of forming the same (2025-09-30),
3. 12376361 - Capping layers in metal gates of transistors (2025-07-29),
4. 12354876 - Gate structure passivating species drive-in method and structure formed thereby (2025-07-08),
5. 12294022 - Semiconductor device and method of manufacturing the same (2025-05-06),
6. 12255104 - Semiconductor device and method of manufacture (2025-03-18),
7. 12237228 - Semiconductor device and method (2025-02-25),
8. 12183629 - Selective hybrid capping layer for metal gates of transistors (2024-12-31),
9. 12176251 - Semiconductor device with profiled work-function metal gate electrode and method of making (2024-12-24),
10. 12170202 - Formation and in-situ etching processes for metal layers (2024-12-17),
11. 12142530 - Semiconductor device and method of manufacture (2024-11-12),
12. 12100751 - Void elimination for gap-filling in high-aspect ratio trenches (2024-09-24),
13. 12087767 - Method of tuning threshold voltages of transistors (2024-09-10),
14. 12040235 - Semiconductor device and method of manufacture (2024-07-16),
15. 11961768 - CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same (2024-04-16),

Title: The Innovative Journey of Hsien-Ming Lee

Introduction:

Hsien-Ming Lee, a pioneering inventor hailing from Changhua, Taiwan, has made significant contributions to the field of technology with his groundbreaking inventions and patents.

Latest Patents:

Lee's latest patents showcase his commitment to innovation, with a focus on advancements in renewable energy technologies and sustainable solutions for a greener future.

Career Highlights:

Throughout his illustrious career, Hsien-Ming Lee has been at the forefront of technological innovation, with a keen focus on developing cutting-edge solutions that have the potential to revolutionize industries.

Collaborations:

Lee has collaborated with leading research institutions, universities, and companies to further his inventions and bring them to market, showcasing his ability to work across disciplines and sectors to drive progress.

Conclusion:

In conclusion, Hsien-Ming Lee's dedication to innovation and his relentless pursuit of technological advancement have solidified his position as a trailblazer in the world of inventions. His work continues to inspire future generations of inventors to push the boundaries of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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