Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsien-Ming Lee

Hung-Chin Chung

Chien-Hao Chen

Da-Yuan Lee

Chung-Chiang Wu

Hsiao-Kuan Wei

Tsung-Ta Tang

Pin-Hsuan Yeh

Chia-Ching Lee

Chin-You Hsu

Chi On Chui

Syun-Ming Jang Jang

Weng Chang

Yi-Ting Wang

Chih-Hsiang Fan

Jing-Cheng Lin

Shing-Chyang Pan

Po-Chin Kuo

Ching-Hua Hsieh

Cheng-Lin Huang

Kuan-Ting Liu

Wei-Chin Lee

Wei-Jen Lo

Jui-Fen Chien

Shau-Lin Shue

Chun-Chieh Wang

Huai-Tei Yang

Yueh-Ching Pai

Po-Yu Lin

Hsin-Yun Hsu

Chi-Yu Chou

Po-Cheng Chen

Chi-Jen Yang

Kuo-Chan Huang

Huan-Just Lin

Kuo-Feng Yu

Hung-Wen Su

Sheng-Liang Pan

Yu-Sheng Wang

Jian-Hao Chen

Chao-Hsien Peng

Chia-Wei Chen

Shih-Hang Chiu

Li-Lin Su

Shao-Jyun Wu

Ya-Wen Chiu

Hsin-Han Tsai

Chih-Yu Hsu

Kun-Wa Kuok

Hung-Chi Wu

Tsung-Han Shen

Kai-Cyuan Yang

Chen-Hua Douglas Yu

Mong-Song Liang

Chung-Liang Cheng

Cheng-Lung Hung

Ching-Hwanq Su

Chia-Lin Hsu

Minghsing Tsai

Ji-Cheng Chen

Jia-Ming Lin

Hsuan-Yu Tung

Shiang-Rung Tsai

Cheng-Chang Wei

Kuan-Chang Chiu

Shao-Lin Shue

Chung Ta Chen

Chung-Shi Liu

Wen-Chih Chiou

Ming-Hsing Tsai

Tsu Shih

Ting-Chu Ko

Shih-Wei Chou

Han-Hsin Kuo

Pohan Kung

Kuo-Wei Cheng

Shing-Chuang Pan

Kevin Chang

Yu-Ming Li

A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Metal gate structure and method of forming the same

A method of forming a semiconductor device includes forming a gate electrode in a wafer. The formation of the gate electrode includes depositing a work-function layer, after the work-function layer is deposited, performing a treatment on the wafer, wherein the treatment is performed by soaking the wafer using a silicon-containing gas; after the treatment, forming a metal capping layer over the work-function layer; and depositing a filling metal over the metal capping layer.

Capping layers in metal gates of transistors

Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Gate structure passivating species drive-in method and structure formed thereby

Provided is a semiconductor device including a first transistor of a first type comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second transistor of the first type comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.

Semiconductor device and method of manufacturing the same

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Semiconductor device and method of manufacture

An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Semiconductor device and method

A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Selective hybrid capping layer for metal gates of transistors

The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Semiconductor device with profiled work-function metal gate electrode and method of making

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Formation and in-situ etching processes for metal layers

Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Void elimination for gap-filling in high-aspect ratio trenches

A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Method of tuning threshold voltages of transistors

A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same

A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Gate resistance reduction through low-resistivity conductive layer

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Changhua, Taiwan

Hsien-Ming Lee