The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Aug. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Ching Lee, New Taipei, TW;

Hsin-Han Tsai, Hsinchu, TW;

Shih-Hang Chiu, Taichung, TW;

Tsung-Ta Tang, Hsinchu, TW;

Chung-Chiang Wu, Taichung, TW;

Hung-Chin Chung, Pingzhen, TW;

Hsien-Ming Lee, Changhua, TW;

Da-Yuan Lee, Jhubei, TW;

Jian-Hao Chen, Hsinchu, TW;

Chien-Hao Chen, Chuangwei Township, TW;

Kuo-Feng Yu, Zhudong Township, TW;

Chia-Wei Chen, Hsinchu, TW;

Chih-Yu Hsu, Xinfeng Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/40 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 27/0886 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01);
Abstract

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.


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