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For the Inventor, By the Inventor

Taichung, Taiwan

Chung-Chiang Wu

This inventor holds 64 USPTO granted patents and 14 published patent applications, primarily in Semiconductor Devices (CPC class H01L). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chung-Chiang Wu. Retrieved from https://idiyas.com/inventor/chung-chiang-wu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 64 

% Patents Active = 98.4

Average Co-Inventor Count = 5.7

ph-index = 5

Forward Citations = 99(Granted Patents)

Forward Citations (Not Self Cited) = 54(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Taipei, TW (2017)
  • Hsin-Chu, TW (2018)
  • Taichung, TW (2017 - 2024)

Company Filing History:

goldMedal63 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal1 out of 481 
 
Taiwan Semiconductor Manufacturing Co., Ltd.
 patents

Years Active: 2017-2026

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Areas of Expertise:
FinFET Structures
Threshold Voltage Tuning
Metal Gate Technology
Semiconductor Manufacturing
Work Function Layer
Capping Layer
Contact Plug
Doped Layers
Geometry Tuning
Low-Resistivity Layer
FET Technology
Transistor Design
64 patents (USPTO):Explore Patents
1. 12733199 - Gate resistance reduction through low-resistivity conductive layer (2026-09-08),
2. 12575154 - Methods for pre-deposition treatment of a work-function metal layer (2026-03-10),
3. 12356656 - FinFET structures and methods of forming the same (2025-07-08),
4. 12336244 - Metal caps for gate structures (2025-06-17),
5. 12310078 - Method of forming metal gate fin electrode structure by etching back metal fill (2025-05-20),
6. 12300733 - Semiconductor device with a work function layer having an oxygen-blocking dopant layer (2025-05-13),
7. 12272556 - Method of manufacturing a semiconductor device with a work-function layer having a concentration of fluorine (2025-04-08),
8. 12255104 - Semiconductor device and method of manufacture (2025-03-18),
9. 12183638 - In-situ formation of metal gate modulators (2024-12-31),
10. 12183629 - Selective hybrid capping layer for metal gates of transistors (2024-12-31),
11. 12148810 - Semiconductor device and method (2024-11-19),
12. 12142531 - Pre-deposition treatment for FET technology and devices formed thereby (2024-11-12),
13. 12142530 - Semiconductor device and method of manufacture (2024-11-12),
14. 12087767 - Method of tuning threshold voltages of transistors (2024-09-10),
15. 12087637 - Semiconductor device and method of manufacture (2024-09-10),

Title: The Innovative Journey of Inventor Chung-Chiang Wu

Introduction: Chung-Chiang Wu, a talented inventor hailing from Taichung, Taiwan, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents: Chung-Chiang Wu's latest patents include advancements in renewable energy technology, smart home devices, and medical equipment, showcasing his diverse range of expertise and creativity.

Career Highlights: With a career spanning over two decades, Chung-Chiang Wu has established himself as a pioneer in the tech industry, holding numerous patents and receiving recognition for his innovative solutions to complex problems.

Collaborations: Throughout his career, Chung-Chiang Wu has collaborated with leading research institutions, universities, and tech companies to further develop and implement his inventions, demonstrating his commitment to pushing the boundaries of technological advancement.

Conclusion: Chung-Chiang Wu's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a visionary inventor, shaping the future of technology and inspiring the next generation of innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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