Jhudong, Taiwan

Hsiang-Huan Lee

This inventor holds 66 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Manufacturing (CPC class H01L). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Other. Active years: 2011-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsiang-Huan Lee. Retrieved from https://idiyas.com/inventor/hsiang-huan-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 66 

% Patents Active = 53.0

Average Co-Inventor Count = 4.0

ph-index = 8

Forward Citations = 266(Granted Patents)

Forward Citations (Not Self Cited) = 242(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Jhudong, TW (2012)
  • Jhodong Township, TW (2014 - 2016)
  • Hsinchu, TW (2015 - 2017)
  • Jhudong Township, Hsinchu County, TW (2011 - 2019)
  • Hsinchu County, TW (2015 - 2021)
  • Jhudong Township, TW (2014 - 2024)

Company Filing History:


Years Active: 2011-2026

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Areas of Expertise:
Conductor Nanowires
Semiconductor Fabrication
Copper Etching
Lithography Techniques
Interconnect Structures
Metallization Systems
Dual Damascene
Chemical-Mechanical Planarization
Recess-Free Structures
Back End of Line
Flexible Buffer Layers
Integrated Circuits
66 patents (USPTO):Explore Patents

Title: Hsiang-Huan Lee: A Pioneer in Semiconductor Innovations

Introduction

Hsiang-Huan Lee, located in Jhudong, Taiwan, has established himself as a leading inventor in the field of semiconductor technology. With an impressive portfolio of 65 patents, Lee has made significant contributions to innovations that enhance the functionality and efficiency of semiconductor devices.

Latest Patents

Among his latest inventions is the patent for the "Selective Formation of Conductor Nanowires." This method encompasses etching a mandrel layer to create mandrel strips, followed by the selective deposition of metal lines on the sidewalls of these strips. To ensure precision during the selective deposition, top surfaces of the mandrel strips are effectively masked by dielectric masks. The innovation further includes the removal of the mandrel layer and dielectric masks, filling the spaces between metal lines with dielectric material, forming via openings, and subsequently filling these openings with a conductive material to establish vias.

Another noteworthy patent is related to a "Method of Semiconductor Integrated Circuit Fabrication." This method outlines the process of fabricating a semiconductor integrated circuit (IC) by providing a substrate and applying a conductive layer. Following this, a patterned hard mask and a catalyst layer are formed. The method also involves growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and utilizing them, along with the patterned hard mask, to etch the conductive layer, thus forming intricate metal features.

Career Highlights

Hsiang-Huan Lee's career includes significant tenure at Taiwan Semiconductor Manufacturing Company (TSMC), where he has been instrumental in advancing semiconductor technologies. His expertise and innovative thinking have played a crucial role in the development of next-generation semiconductor solutions.

Collaborations

Throughout his career, Lee has collaborated with notable professionals in the field, including Shau-Lin Shue and Chao-Hsien Peng. These collaborations have fostered an environment of shared knowledge and innovation, further amplifying his impact on the semiconductor industry.

Conclusion

Hsiang-Huan Lee continues to push the boundaries of semiconductor innovation with his pioneering patents. His work not only enhances the capabilities of electronic devices but also sets a foundation for future developments in semiconductor technology. As he progresses in his career, the industry eagerly anticipates his next contributions and advances.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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