The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Nov. 26, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chao-Hsien Peng, Zhubei, TW;

Chi-Liang Kuo, Hsin-Chu, TW;

Hsiang-Huan Lee, Jhudong Township, TW;

Shau-Lin Shue, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/47 (2006.01); H01L 21/31 (2006.01); H01L 21/44 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/76823 (2013.01); H01L 21/76829 (2013.01); H01L 21/76831 (2013.01); H01L 21/76841 (2013.01); H01L 21/76843 (2013.01); H01L 21/76862 (2013.01); H01L 21/76867 (2013.01); H01L 21/76874 (2013.01); H01L 21/76883 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/53233 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.


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