Hsinchu, Taiwan

Shau-Lin Shue

This inventor holds 385 USPTO granted patents and 67 published patent applications, primarily in Semiconductor Interconnects (CPC class H01L23-5226). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 1998-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shau-Lin Shue. Retrieved from https://idiyas.com/inventor/shau-lin-shue

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 385 

% Patents Active = 80.5

Average Co-Inventor Count = 3.8

ph-index = 24

Forward Citations = 5,903(Granted Patents)

Forward Citations (Not Self Cited) = 5,366(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Hsinchu, CN (2000)
  • Hsinchu City, TW (2008)
  • Hsincu, TW (2017)
  • Hsin-chu, TW (1998 - 2024)

Company Filing History:


Years Active: 1998-2026

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Areas of Expertise:
Graphene Barrier Layer
Interconnect Structure
Air Gap Structure
Selective Deposition
Thermal Conductive Layer
Self-Aligned Via
Low Capacitance Metallization
Chemical-Mechanical Polishing
Semiconductor Packaging
Conductive Nanowires
Heat Dissipation
Trench Distortions
385 patents (USPTO):Explore Patents

Title: Shau-Lin Shue: Advancing Semiconductor Technologies through Innovation

Introduction:

Throughout his illustrious career, Shau-Lin Shue has made significant contributions to the field of semiconductor technologies. Hailing from Hsinchu, Taiwan, Shue has garnered accolades for his exceptional work and has been instrumental in advancing the capabilities of integrated circuits. This article explores his latest patents, highlights his remarkable career achievements, and sheds light on his collaborations with industry peers.

Latest Patents:

Shue's inventive prowess is evidenced by his extensive patent portfolio, which currently stands at an impressive 291 patents. Two of his recent patents highlight his innovative approach to enhancing the stability and performance of semiconductor structures.

1. Dielectric Capping Structure Overlying a Conductive Structure to Increase Stability:

One of Shue's recent patents focuses on a semiconductor structure that employs a dielectric capping layer to enhance the stability of a conductive wire within a first dielectric structure. By adding an etch stop layer and an upper dielectric layer, this structure exhibits improved performance and reliability.

2. Semiconductor Structure Including Low-Resistance Interconnect and Integrated Circuit Device Having the Same:

In this patent, Shue presents a method for fabricating integrated circuit devices with low-resistance interconnects. By selectively depositing a blocking layer, the etch stop layer, and a second metal feature, this method ensures the electrical coupling of multiple metal features, resulting in enhanced circuit performance.

Career Highlights:

Shue's remarkable contributions have made a significant impact on the semiconductor industry. His groundbreaking work has not only pushed the boundaries of technological innovation but has also earned him widespread recognition.

Collaborations:

Shue has collaborated closely with esteemed colleagues in his pursuit of advancing semiconductor technologies. Notably, he has collaborated with Ming-Han Lee and Chung-Ju Lee, both distinguished professionals in the field. Together, they have leveraged their expertise to develop cutting-edge solutions and drive progress in the industry.

Conclusion:

Shau-Lin Shue's career as a semiconductor innovator has been marked by significant milestones and commendations. His numerous patents and inventive methods have propelled the field forward and made a lasting impact on the semiconductor industry. Shue's collaborations with esteemed peers further highlight his commitment to collaboration and knowledge sharing. As we look to the future, it is exciting to anticipate further breakthroughs from this outstanding innovator.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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