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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12696744 B1

PDFFull Text
Date of Patent:
Jul. 28, 2026

Filed:

Nov. 20, 2023

Multi-metal fill with self-aligned patterning and dielectric with voids

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tai-I Yang, Hsinchu City, TW;

Wei-Chen Chu, Taichung City, TW;

Hsiang-Wei Liu, Tainan City, TW;

Shau-Lin Shue, Hsinchu, TW;

Li-Lin Su, Taichung County, TW;

Yung-Hsu Wu, Taipei City, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Sterne, Kessler, Goldstein & Fox P.L.L.C.

Primary Examiner:

Nilufa Rahim

Int. Cl.
CPC ...
H10F 77/50 (2025.01); H10W 20/00 (2026.01); H10W 20/46 (2026.01);
U.S. Cl.
CPC ...
H10W 20/084 (2026.01); H10W 20/063 (2026.01); H10W 20/069 (2026.01); H10W 20/072 (2026.01); H10W 20/098 (2026.01); H10W 20/46 (2026.01); H10W 20/037 (2026.01);
Abstract

Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Find Patent Forward Citations

Yang, Tai-I. (2026). Multi-metal fill with self-aligned patterning and dielectric with voids (U.S. Patent No. 12696744). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12696744

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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